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MC14504B Hex Level Shifter for TTL to CMOS or CMOS to CMOS
The MC14504B is a hex non-inverting level shifter using CMOS technology. The level shifter will shift a TTL signal to CMOS logic levels for any CMOS supply voltage between 5 and 15 volts. A control input also allows interface from CMOS to CMOS at one logic level to another logic level: Either up or down level translating is accomplished by selection of power supply levels VDD and VCC. The VCC level sets the input signal levels while VDD selects the output voltage levels.
http://onsemi.com MARKING DIAGRAMS
16 PDIP-16 P SUFFIX CASE 648 MC14504BCP AWLYYWW 1 16 SOIC-16 D SUFFIX CASE 751B 1 16 TSSOP-16 DT SUFFIX CASE 948F 14 504B ALYW 1 16 SOEIAJ-16 F SUFFIX CASE 966 1 - 0.5 to VDD + 0.5 10 500 - 55 to +125 - 65 to +150 260 V mA mW C C C A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week MC14504B AWLYWW 14504B AWLYWW
* UP Translates from a Low to a High Voltage or DOWN Translates * * * * *
from a High to a Low Voltage Input Threshold Can Be Shifted for TTL Compatibility No Sequencing Required on Power Supplies or Inputs for Power Up or Power Down 3 to 18 Vdc Operation for VDD and VCC Diode Protected Inputs to VSS Capable of Driving Two Low-Power TTL Loads or One Low-Power Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol VCC VDD Vin Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range DC Supply Voltage Range Input Voltage Range (DC or Transient) Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 3.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value - 0.5 to +18.0 - 0.5 to +18.0 - 0.5 to +18.0 Unit V V V
ORDERING INFORMATION
Device MC14504BCP MC14504BD MC14504BDR2 MC14504BDT MC14504BF MC14504BFEL Package PDIP-16 SOIC-16 SOIC-16 TSSOP-16 SOEIAJ-16 SOEIAJ-16 Shipping 2000/Box 48/Rail 2500/Tape & Reel 96/Rail See Note 1. See Note 1.
2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
v
v
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
(c) Semiconductor Components Industries, LLC, 2000
1
March, 2000 - Rev. 3
Publication Order Number: MC14504B/D
MC14504B
PIN ASSIGNMENT
VCC Aout Ain Bout Bin Cout Cin VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Fout Fin MODE Eout Ein Dout Din
LOGIC DIAGRAM
VCC VDD
INPUT
LEVEL SHIFTER
OUTPUT
MODE
TTL/CMOS MODE SELECT
Mode Select 1 (VCC) 0 (VSS) 1/6 of package shown.
Input Logic Levels TTL CMOS
Output Logic Levels CMOS CMOS
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4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Quiescent Current (Per Package) TTL-CMOS Mode
Quiescent Current (Per Package) TTL-CMOS Mode
Quiescent Current (Per Package) CMOS-CMOS Mode
Input Capacitance (Vin = 0)
Input Current
Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)
Input Voltage "1" Level (VOH = 9.0 Vdc) TTL-CMOS (VOH = 13.5 Vdc) TTL-CMOS (VOH = 9.0 Vdc) CMOS-CMOS (VOH = 13.5 Vdc) CMOS-CMOS (VOH = 13.5 Vdc) CMOS-CMOS
Input Voltage "0" Level (VOL = 1.0 Vdc) TTL-CMOS (VOL = 1.5 Vdc) TTL-CMOS (VOL = 1.0 Vdc) CMOS-CMOS (VOL = 1.5 Vdc) CMOS-CMOS (VOL = 1.5 Vdc) CMOS-CMOS
Output Voltage Vin = 0 V
(VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc)
Vin = VCC
Characteristic
"0" Level
"1" Level
Source
Sink
Symbol
IDD or ICC
VOH
VOL
IOH
VIH
ICC
IDD
Cin
IOL
VIL
Iin
VCC Vdc
5.0 5.0 5.0
5.0 5.0 5.0
5.0 5.0 5.0 5.0 10
5.0 5.0 5.0 5.0 10
-- -- --
--
--
-- -- --
-- -- -- --
-- -- --
-- -- --
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MC14504B
VDD Vdc
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 5.0 10 15
5.0 10 15
5.0 10 15
15
10 15 10 15 15
10 15 10 15 15
--
3 - 3.0 - 0.64 - 1.6 - 4.2 4.95 9.95 14.95 0.64 1.6 4.2 Min 2.0 2.0 3.6 3.6 7.1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 55_C 0.1 0.05 0.10 0.20 0.05 0.05 0.05 Max 5.0 5.0 5.0 0.5 1.0 2.0 0.8 0.8 1.5 1.5 3.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 4.95 9.95 14.95 0.51 1.3 3.4 Min 2.0 2.0 3.5 3.5 7.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.00001 Typ 0.0005 0.0010 0.0015 0.0005 0.0010 0.0015 - 4.2 - 0.88 - 2.25 - 8.8 25_C 1.5 1.5 2.75 2.75 5.5 1.3 1.3 2.25 2.25 4.5 0.88 2.25 8.8 5.0 5.0 10 15 0 0 0 2.5 2.5 2.5
(4.)
0.1
0.05 0.10 0.20
0.05 0.05 0.05
Max
5.0 5.0 5.0 0.5 1.0 2.0 7.5 0.8 0.8 1.5 1.5 3.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- 1.7 - 0.36 - 0.9 - 2.4
4.95 9.95 14.95
0.36 0.9 2.4
Min
2.0 2.0 3.5 3.5 7.0
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
125_C
1.0
0.05 0.05 0.05
Max
6.0 6.0 6.0 3.8 7.5 15 1.5 3.0 6.0 0.8 0.8 1.4 1.5 2.9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
mAdc mAdc mAdc Adc Adc Adc Unit Vdc Vdc Vdc Vdc pF
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II II I IIIIIIIIIIIIIIIIIIII I II III II II II II II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I I I I I II II II II II II II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II II II II I II II II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I II II II II II II II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII III II II I I IIIIIIIIIIIIIIIIIIII I II II II II II II II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II I III I I I I I II II II II II II II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II II I II II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
5. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. Output Rise and Fall Time Propagation Delay, Low to High Propagation Delay, High to Low
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)
Characteristic
tTLH, tTHL
Symbol
tPLH
tPHL
CMOS - CMOS VCC > VDD
CMOS - CMOS VDD > VCC
CMOS - CMOS VCC > VDD
CMOS - CMOS VDD > VCC
Shifting Mode
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TTL - CMOS VDD > VCC TTL - CMOS VDD > VCC
MC14504B
ALL
4 VCC Vdc 5.0 5.0 10 5.0 5.0 5.0 5.0 10 5.0 5.0 10 15 15 10 15 15 -- -- -- VDD Vdc 5.0 10 15 5.0 5.0 10 5.0 5.0 10 10 15 15 10 15 10 15 15 10 15 Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ (5.) Limits 100 50 40 275 275 145 170 170 100 170 160 185 185 175 120 120 70 140 140 Max 200 100 80 550 550 290 340 340 200 340 320 370 370 350 240 240 140 280 280 Unit ns ns ns
MC14504B
7 VSp , INPUT SWITCHPOINT VOLTAGE (Vdc) 6 5 4 3 2 1 0 0 5 10 15 VDD, SUPPLY VOLTAGE (Vdc) 20 VCC = 5 V VCC = 10 V VSp , INPUT SWITCHPOINT VOLTAGE (Vdc) 7 6 5 4 3 2 1 0 0 5 10 15 VDD, SUPPLY VOLTAGE (Vdc) 20 VCC = 5 V
Figure 1. Input Switchpoint CMOS to CMOS Mode
20
Figure 2. Input Switchpoint TTL to CMOS Mode
20
VDD, SUPPLY VOLTAGE (Vdc)
10
VDD, SUPPLY VOLTAGE (Vdc)
15
15
10
5
5
0 0
0 20 0 5 10 15 VCC, SUPPLY VOLTAGE (Vdc) 20
5 10 15 VCC, SUPPLY VOLTAGE (Vdc)
Figure 3. Operating Boundary CMOS to CMOS Mode
Figure 4. Operating Boundary TTL to CMOS Mode
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EE EE EE EE EE EE EE EE
EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE
MC14504B
PACKAGE DIMENSIONS
-A-
16 9
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
-A-
SOIC-16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
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MC14504B
PACKAGE DIMENSIONS
TSSOP-16 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N J
N 0.25 (0.010) 0.15 (0.006) T U
S
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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EEE CCC EEE CCC
M
-W-
MC14504B
PACKAGE DIMENSIONS
SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE O
LE Q1 E HE
1 8
16
9
M_ L DETAIL P
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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PUBLICATION ORDERING INFORMATION
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MC14504B/D

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